1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a built-in self-test circuit which has both a function for giving a reset time-period required to reset a synchronization circuit of the built-in self-test circuit and a function for producing a test signal to be used to test a tested circuit.
2. Description of Related Art
A built-in test method for performing a self-test of a to-be tested circuit by using a self-test circuit built in a semiconductor chip has been recently paid attention. This self-test circuit has normally a synchronization circuit in which a test signal is produced. To stably output the test signal produced in the synchronization signal to the to-be-tested circuit, it is required to reset the synchronization circuit before the outputting of the test signal. To reset the synchronization circuit, a reset time-period equal to or longer than the one clock of a clock signal is required.
FIG. 11 is a block diagram of a self-test circuit of a conventional semiconductor integrated circuit. As shown in FIG. 11, a reference numeral 111 indicates a synchronization circuit, a reference numeral 112 indicates a self-test circuit including the synchronization circuit 111.
Next, an operation of the conventional semiconductor circuit having the self-test circuit 112 is described with reference to FIG. 12.
FIG. 12 is a timing chart of control signals used in the self-test circuit 112 shown in FIG. 11. In FIG. 12, a symbol EXTCLK (or BISTFCLK) denotes an external clock signal supplied from the outside, symbols ACTCE and ACTLE denote enabling signals, and a symbol INTCLK denotes an internal clock signal.
As shown in FIG. 12, when a level of an enabling signal ACTCE is changed to a high (H) level, an external clock signal EXTCLK (or BISTFCLK) passes through inverters and is supplied to the synchronization circuit 111 as an internal clock signal INTCLK. Therefore, an operation of the synchronization circuit 111 is started. That is, the synchronization circuit 111 is reset according to the internal clock signal INTCLK during a low (L) level of another enabling signal ACTLE (a time-period T121). When a level of the enabling signal ACTLE is changed to the H level after the internal clock signal INTCLK is supplied to the synchronization circuit 111, the synchronization circuit 111 is set to an enabling condition, a test signal set to the H level is produced in the synchronization circuit 111, and the test signal is transmitted to an AND gate. Also, the enabling signal ACTLE set to the H level is supplied to the AND gate, so that the test signal passes through the AND gate and is supplied to a to-be-tested circuit (not shown) such as a static random access memory or a dynamic random access memory (indicated by SDRAM).
As is described above, the reset time-period T121 of the synchronization circuit 111 is obtained according to the two enabling signals ACTCE and ACTLE in the conventional semiconductor integrated circuit.
However, because the two enabling signals ACTCE and ACTLE differ from each other, in cases where the level change of the enabling signal ACTCE is delayed, there is a drawback that the reset time-period T121 required to reset the synchronization circuit 111 cannot be obtained. Also, because the enabling signals ACTCE and ACTLE are required, two wiring areas of the enabling signals ACTCE and ACTLE lead from the outsides are required. Therefore, there is another drawback that a layout area of the semiconductor chip cannot be efficiently used.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor integrated circuit, a semiconductor integrated circuit having a built-in test circuit in which a reset time-period equal to or more than a prescribed number of clocks required to reset a synchronization circuit is reliably obtained while efficiently using a circuit area of the semiconductor integrated circuit.
The object is achieved by the provision of a semiconductor integrated circuit having a built-in self-test circuit, comprising:
a control signal producing circuit for receiving an external clock signal, receiving a first enabling signal which is asynchronous with the external clock signal and has a level change occurring just after or just before a particular level change of the external clock signal, producing a second enabling signal synchronous with the external clock signal on condition that a level of the second enabling signal is risen at a time which is later than a time of the particular level change of the external clock signal by a prescribed number of clocks of the external clock signal, and outputting the second enabling signal;
a synchronization circuit for receiving the external clock signal according to the level change of the first enabling signal, performing a reset operation in a reset time-period from the time of the particular level change of the external clock signal to the level rising time of the second enabling signal, receiving the second enabling signal produced by the control signal producing circuit, and producing a test signal synchronized with the external clock signal according to the second enabling signal; and
first arithmetic logic means for receiving the second enabling signal produced by the control signal producing circuit and the test signal produced by the synchronization circuit, performing a logical multiply operation for the second enabling signal and the test signal to obtain the test signal as a result of the logical multiply operation, and outputting the test signal obtained as a result of the logical multiply operation to a to-be-self-tested circuit.
In the above configuration, a second enabling signal synchronized with an external clock signal is produced by the control signal producing circuit according to the external clock signal and a first enabling signal asynchronous with the external clock signal. In this case, though a level of the second enabling signal is risen according to the level change of the first enabling signal occurring just after or just before the particular level change of the external clock signal, a level rising change of the second enabling signal is delayed, so that the reset time-period from the time of the particular level change of the external clock signal to the time of the level rising change of the second enabling signal is obtained.
Also, a reset operation is performed in the synchronization circuit in the reset time-period, so that the synchronization circuit itself is reset. After the reset time-period passes, a risen level of the second enabling signal is received in the synchronization circuit, and a test signal synchronized with the external clock signal is produced according to the second enabling signal.
Thereafter, a logical multiply operation is performed by the first arithmetic logic means for the second enabling signal and the test signal, and the test signal is obtained as a result of the logical multiply operation. Therefore, the to-be-self-tested circuit can be self-tested according to the test signal.
Accordingly, the reset time-period equal to or more than a prescribed number of clocks of the external clock signal can be reliably obtained, the synchronization circuit can be reliably reset in the reset time-period, and the test signal synchronized with the external clock signal can be stably output.
Also, because the second enabling signal is produced from the first enabling signal and the external clock signal, a wiring for leading the second enabling signal to the built-in self-test circuit is not required, so that a circuit area of the semiconductor integrated circuit can be efficiently used.
It is preferred that the control signal producing circuit comprises a plurality of latch circuits arranged in series, the first enabling signal is used to set the latch circuits to an enabling condition, and the second enabling signal synchronized with the external clock signal is produced in the latch circuits set to the enabling condition according to the first enabling signal.
In the above configuration, the reset time-period is obtained by delaying an output signal of each latch circuit in the latch circuit. Therefore, the reset time-period can be reliably obtained.
It is also preferred that the control signal producing circuit comprises:
a first system latch circuit having a plurality of first latch circuits arranged in series;
a second system latch circuit having a plurality of second latch circuits arranged in series;
second arithmetic logic means for performing a logical multiply for an output signal of the first system latch circuit and an output signal of the second system latch circuit; and
a third latch circuit for latching an arithmetic result signal of the second arithmetic logic means to delay the arithmetic result signal and outputting the delayed arithmetic result signal as the second enabling signal synchronized with the external clock signal, the first enabling signal is used to set the first latch circuits of the first system latch circuit to an enabling condition, the level of the first enabling signal changing just before the particular level change of the external clock signal is latched in synchronization with the particular level change of the external clock signal in the first latch circuit placed on the first stage of the first system latch circuit, the first enabling signal is used to set the second latch circuits of the second system latch, circuit to an enabling condition, and the level of the first enabling signal changing just after the particular level change of the external clock signal is latched in synchronization with a level change next to the particular level change of the external clock signal in the second latch circuit placed on the first stage of the second system latch circuit.
In the above configuration, the level of the first enabling signal changing just before the particular level change of the external clock signal is latched in synchronization with the particular level change of the external clock signal in the first latch circuit placed on the first stage of the first system latch circuit, and the level of the first enabling signal changing just after the particular level change of the external clock signal is latched in synchronization with a level change next to the particular level change of the external clock signal in the second latch circuit placed on the first stage of the second system latch circuit.
Accordingly, regardless of whether the level change of the first enabling signal occurs just after or just before the particular level change of the external clock signal, the reset time-period from the time of the particular level change of the external clock signal to the level rising time of the second enabling signal can be reliably obtained.
It is also preferred that the control signal producing circuit comprises:
a selector circuit, connected with the third latch circuit, for maintaining the level of the second enabling signal to a low level until the level of the arithmetic result signal of the second arithmetic logic means is changed to a high level, and outputting the second enabling signal set to a high level after the reset time-period passes.
In the above configuration, the level of the second enabling signal is maintained to a low level until the level of the arithmetic result signal of the second arithmetic logic means is changed to a high level.
Accordingly, the test signal can be stably and reliably sent to the to-be-self-tested circuit after the reset time-period passes.
It is also preferred that the control signal producing circuit further comprises:
a counter, arranged between the second arithmetic logic means and the third latch circuit, for delaying the arithmetic result signal of the second arithmetic logic means by a second prescribed number of clocks of the external clock signal to prolong the reset time-period, and outputting the delayed arithmetic result signal to the third latch circuit.
In the above configuration, the arithmetic result signal is delayed in the counter. Therefore, the reset time-period determined in the first system latch circuit, the second system latch circuit and the third latch circuit can be arbitrarily adjusted, and the reset time-period arbitrarily adjusted is useful for synchronization circuits in which various reset time-periods are required.
It is also preferred that the semiconductor integrated circuit having the built-in self-test circuit further comprises a clock signal supplying circuit for supplying the external clock signal to the synchronization circuit and the control signal producing circuit and supplying an internal clock signal to the to-be-self-tested circuit, wherein the clock signal supplying circuit comprises:
a first logical circuit for receiving the external clock signal and outputting the external clock signal to the to-be-self-tested circuit as the internal clock signal in cases where the first enabling signal is set to a first level; and
a second logical circuit for receiving the external clock signal and the first enabling signal and outputting the external clock signal to the synchronization circuit and the control signal producing circuit in cases where the first enabling signal is set to a second level.
In the above configuration, the external clock signal is not sent from the clock signal supplying circuit to the synchronization circuit or the control signal producing circuit in cases where the first enabling signal is set to the first level, but the external clock signal is sent from the second logical circuit of the clock signal supplying circuit to the synchronization circuit and the control signal producing circuit in cases where the first enabling signal is set to the second level.
Accordingly, because the external clock signal is sent to the synchronization circuit and the control signal producing circuit only when the synchronization circuit and the control signal producing circuit require the external clock signal, an electric power consumed in the semiconductor integrated circuit can be reduced.
It is also preferred that the semiconductor integrated circuit having the built-in self-test circuit further comprises
a delaying circuit for delaying the external clock signal output from the second logical circuit of the clock signal supplying circuit to the synchronization circuit by a prescribed time-period to prevent a clock skew between the test signal produced in the synchronization circuit and the internal clock signal output from the first logical circuit of the clock signal supplying circuit.
In the above configuration, the external clock signal output from the second logical circuit of the clock signal supplying circuit to the synchronization circuit and the control signal producing circuit is delayed in the delaying circuit by a prescribed time-period, so that a clock skew between the test signal output from the synchronization circuit and the internal clock signal output from the first logical circuit of the clock signal supplying circuit can be prevented.
Accordingly, a self-test can be correctly performed in the to-be-self-tested circuit according to the test signal and the internal clock signal.